1. Field of the Invention
The present invention generally relates to a flash memory, and more particularly to a method of reducing bit error rate for a flash memory.
2. Description of the Prior Art
Flash memory is a non-volatile solid state memory device that can be electrically erased and reprogrammed, and is a specific type of electrically erasable programmable read-only memory (EEPROM) device. Conventional flash memory stores a single bit of information in each memory cell such that each memory cell can be programmed to assume two possible states. The conventional flash memory is thus commonly referred to as single-level cell (SLC) flash memory or single-bit cell (SBC) flash memory. Modern flash memory is capable of storing two or more bits of information in each memory cell such that each memory cell can be programmed to assume more than two possible states. The modern flash memory is thus commonly referred to as multi-level cell (MLC) flash memory or multi-bit cell (MBC) flash memory.
In the MLC flash memory, data of different state are programmed to the flash memory by storing different amount of charge in the floating gate of the flash memory. As the charge in the floating gate specifically determines the corresponding threshold voltage, the data can then be read from the MLC flash memory according to their different threshold voltage. Due to variations among the memory cells during the manufacture, operation or according to other factors, the threshold voltage of each state is not a constant value but a range. When the flash memory is being read, the threshold voltage of a cell is compared to read voltages to determine its state.
The read voltages for reading data from the traditional MLC flash memory are constant. In practice, however, the threshold voltage distribution may probably shift after the flash memory has been subjected to a predetermined number of program/erase cycles or/and a predetermined data retention time has elapsed. Furthermore, due to coupling effect caused by neighboring page or pages, the distribution may widen sufficiently such that neighboring states may partially overlap. For example, as shown in FIG. 1 (in which only two states are concerned and shown for illustrative purpose), the initial distribution 10 with read voltage Th0 may be suffered from retention issue after a long time not going through program/erase cycle, and therefore drifted downward to a shifted distribution 12 with a new read voltage Th1. Furthermore, the neighboring states of the shifted distribution 12 partially overlap, resulting in error bits. If the extent of the overlapping is large, error correction control (ECC) may not be capable of correcting the error bits.
For the reason that conventional MLC or SLC flash memory could probably result in read errors due to coupling effect, a need has arisen to propose some novel schemes to reduce bit error rate for the flash memory.